1. Field of the Invention
The present invention relates to MOS transistor gate structures and, more particularly, to a photolithographic-less, nano-technology gate structure with very low resistivity.
2. Description of the Related Art
MOS transistors are well-known semiconductor circuit elements. FIGS. 1A-1D show cross-sectional views that illustrate a prior-art method of forming MOS transistors. As shown in FIG. 1A, the method utilizes a semiconductor wafer 100 that has been conventionally formed to have a shallow trench isolation region STI that forms a number of laterally-isolated surface regions.
As further shown in FIG. 1A, the method begins by forming a gate insulation layer 110 on the top surface of semiconductor wafer 100, followed by the formation of an overlying polysilicon layer 112. After layer 112 has been formed, a mask 114 is formed and patterned on the top surface of layer 112.
Following this, as shown in FIG. 1B, the exposed regions of polysilicon layer 112 are etched until the exposed regions have been removed from the top surface of gate insulation layer 110, thereby forming a number of polysilicon gates 116. Once the etch has been completed, mask 114 is removed.
Next, as shown in FIG. 1C, the exposed surfaces of gate insulation layer 110 and the polysilicon gates 116 are implanted with a dopant, such as boron or phosphorous. The implant both dopes the gates 116 and forms lightly-doped source and drain regions 120 and 122, respectively, in semiconductor wafer 100 on opposite sides of each of the gates 116.
Following this, a layer of isolation material, such as a layer of oxide, is deposited on the exposed surfaces of gate insulation layer 110 and the polysilicon gates 116. As shown in FIG. 1D, once deposited, the layer of isolation material is then anisotropically etched to form side wall spacers 124 that contact the side walls of the gates 116.
After the side wall spacers 124 have been formed, the exposed surfaces of gate insulation layer 110 and the polysilicon gates 116 are again implanted with the dopant. The implant both dopes the gates 116 and forms heavily-doped source and drain regions 126 and 128, respectively, in semiconductor wafer 100 on opposite sides of each of the gates 116.
Thus, at this point in the method, a number of MOS transistors, which each have spaced-apart source and drain regions 120/126 and 122/128, an overlying gate insulation layer 110, and an overlying gate 116, have been formed. Following this, the method continues with conventional steps.
One problem with the prior-art method of forming MOS transistors is that the minimum size of the widths W of the gates 116 is limited to the minimum feature size that is photolithographically obtainable with the fabrication process that is used to form the MOS transistors.
Thus, since the gate widths W can not be reduced below the minimum photolithographic feature size that is obtainable with the fabrication process that is used to form the MOS transistors, the minimum photolithographic feature size limits the maximum number of MOS transistors that can be formed in a defined semiconductor surface region.
As a result, to increase the packing density, there is a need for a method of forming MOS transistors which can form the widths W of the gates to have a size that is substantially less than the minimum feature size that is photolithographically obtainable with the fabrication process that is used to form the MOS transistors.